IC可靠性之Latch-up(閂鎖效應)

Latch up的定義出自JESD78，原文定義如下（出自JESD78E）：

latch-up： A state in which a low-impedance path， resulting from an overstress that triggers a parasitic thyristor structure， persists after removal or cessation of the triggering condition。

NOTE 1 The overstress can be a voltage or current surge， an excessive rate of change of current or voltage， or any other abnormal condition that causes the parasitic thyristor structure to become regenerative。

NOTE 2 Latch-up will not damage the device provided that the current through the low-impedance path is sufficiently limited in magnitude or duration。